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Abstract:
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A concept of wafer tomography is introduced referring to a detailed reconstruction of hidden information on integrated circuits given incomplete and sparse layer-by-layer data that are usually available. Proposed tools associate chip failures with all observed, partially observed, and unobserved defects on a chip via a cause-and-effect relationship. This methodology allows to predict the final yield at any time during the production process, to determine the most probable causes of failures, the most dangerous defects, the most vulnerable layers, the most influential factors, and to suggest optimal yield enhancement strategies. Mathematics of wafer tomography will be explained; computational techniques will be proposed for handling massive data in presence of a large number of parameters.
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